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MATLAB PROJECT TITLES 2013-2014
317. Non locally Centralized Sparse Representation For Image Restoration
Abstract: The sparse representation models code an image patch as a linear combination of a few atoms chosen out from an over-complete dictionary, and they have shown promising results in various image restoration applications. However, due to the degradation of the observed image (e.g., noisy, blurred and/or downsampled), the sparse representations by conventional models may not be accurate enough for a faithful reconstruction of the original image. To improve the performance of sparse representation based image restoration, in this paper the concept of sparse coding noise is introduced, and the goal of image restoration turns to how to suppress the sparse coding noise. To this end, we exploit the image nonlocal self-similarity to obtain good estimates of the sparse coding coefficients of the original image, and then centralize the sparse coding coefficients of the observed image to those estimates. The so-called nonlocally centralized sparse representation (NCSR) model is as simple as the standard sparse representation model, while our extensive experiments on various types of image restoration problems, including denoising, deblurring and super-resolution, validate the generality and state-of-the-art performance of the proposed NCSR algorithm.
Keywords: Sparse representation, image restoration, nonlocal similarity
318. Sparse Representation Based Image Interpolation With Nonlocal Autoregressive Modeling
Abstract: Sparse representation has proven to be a promising approach to image super-resolution, where the low resolution (LR) image is usually modeled as the down-sampled version of its high resolution (HR) counterpart after blurring. When the blurring kernel is the Dirac delta function, i.e., the LR image is directly down-sampled from its HR counterpart without blurring, the super-resolution problem becomes an image interpolation problem. In such case, however, the conventional sparse representation models (SRM) become less effective because the data fidelity term will fail to constrain the image local structures. In natural images, fortunately, the many nonlocal similar patches to a given patch could provide nonlocal constraint to the local structure. In this paper we incorporate the image nonlocal self-similarity into SRM for image interpolation. More specifically, a nonlocal autoregressive model (NARM) is proposed and taken as the data fidelity term in SRM. We show that the NARM induced sampling matrix is less coherent with the representation dictionary, and consequently makes SRM more effective for image interpolation. Our extensive experimental results demonstrated that the proposed NARM based image interpolation method can effectively reconstruct the edge structures and suppress the jaggy/ringing artifacts, achieving the best image interpolation results so far in term of PSNR as well as perceptual quality metrics such as SSIM and FSIM.
Index Terms: Image interpolation, super-resolution, sparse representation, nonlocal autoregressive model.
319.Removing Atmospheric Turbulence Via Space-Invariant De convolution
Abstract: To correct geometric distortion and reduce space and time-varying blur, a new approach is proposed in this paper capable of restoring a single high-quality image from a given image sequence distorted by atmospheric turbulence. This approach reduces the space and time-varying deblurring problem to a shift invariant one. It first registers each frame to suppress geometric deformation through B-spline-based nonrigid registration. Next, a temporal regression process is carried out to produce an image from the registered frames, which can be viewed as being convolved with a space invariant near-diffraction-limited blur. Finally, a blind deconvolution algorithm is implemented to deblur the fused image, generating a final output. Experiments using real data illustrate that this approach can effectively alleviate blur and distortions, recover details of the scene, and significantly improve visual quality.
Index Terms: Image restoration, atmospheric turbulence, nonrigid image registration, point spread function, sharpness metric
320. SAIF-Ly Boost De noising Performance
Abstract: Spatial domain image filters (e.g. bilateral filter, NLM, LARK) have achieved great success in denoising. However, their overall performance has not generally surpassed the leading transform domain based filters (such as BM3D). One important reason is that spatial domain filters lack an efficient way to adaptively fine tune their denoising strength; something that is relatively easy to do in transform domain method with shrinkage operators. In the pixel domain, the smoothing strength is usually controlled globally by, for example, tuning a regularization parameter. In this paper, we propose SAIF1 (Spatially Adaptive Iterative Filtering), a new strategy to control the denoising strength locally for any spatial domain method. This approach is capable of filtering local image content iteratively using the given base filter, while the type of iteration and the iteration number are automatically optimized with respect to estimated risk (i.e. mean-squared error). In exploiting the estimated local SNR, we also present a new risk estimator which is different than the often-employed SURE method and exceeds its performance in many cases. Experiments illustrate that our strategy can significantly relax the base algorithm’s sensitivity to its tuning (smoothing) parameters, and effectively boost the performance of several existing denoising filters to generate state-of-the-art results under both simulated and practical conditions.
Index Terms: Image denoising, spatial domain filter, risk estimator, SURE, pixel aggregation
321. Image Signature: Highlighting Sparse Salient Regions
Abstract: We introduce a simple image descriptor referred to as the image signature. We show, within the theoretical framework of sparse signal mixing, that this quantity spatially approximates the foreground of an image. We experimentally investigate whether this approximate foreground overlaps with visually conspicuous image locations by developing a saliency algorithm based on the image signature. This saliency algorithm predicts human fixation points best among competitors on the Bruce and Tsotsos  benchmark data set and does so in much shorter running time. In a related experiment, we demonstrate with a change blindness data set that the distance between images induced by the image signature is closer to human perceptual distance than can be achieved using other saliency algorithms, pixel-wise, or GIST  descriptor methods.
Index Terms: Saliency, visual attention, change blindness, sign function, sparse signal analysis.
322. Nonparametric Bayesian Dictionary Learning for Analysis of Noisy and Incomplete Images.
Abstract: Nonparametric Bayesian methods are considered for recovery of imagery based upon compressive, incomplete, and/or noisy measurements. A truncated beta-Bernoulli process is employed to infer an appropriate dictionary for the data under test and also for image recovery. In the context of compressive sensing, significant improvements in image recovery are manifested using learned dictionaries, relative to using standard orthonormal image expansions. The compressive-measurement projections are also optimized for the learned dictionary. Additionally, we consider simpler (incomplete) measurements, defined by measuring a subset of image pixels, uniformly selected at random. Spatial interrelationships within imagery are exploited through use of the Dirichlet and probit stick-breaking processes. Several example results are presented, with comparisons to other methods in the literature.
Index Terms: Bayesian nonparametrics, compressive sensing, dictionary learning, factor analysis, image denoising, image interpolation, sparse coding.
323. Patch-Based Near-Optimal Image Denoising
Abstract: In this paper, we propose a denoising method motivated by our previous analysis of the performance bounds for image denoising. Insights from that study are used here to derive
a high-performance practical denoising algorithm. We propose a patch-based Wiener filter that exploits patch redundancy for image denoising. Our framework uses both geometrically and photometrically similar patches to estimate the different filter parameters. We describe how these parameters can be accurately estimated directly from the input noisy image. Our denoising approach, designed for near-optimal performance (in the mean-squared error sense), has a sound statistical foundation that is analyzed in detail. The performance of our approach is
experimentally verified on a variety of images and noise levels. The results presented here demonstrate that our proposed method is on par or exceeding the current state of the art, both visually and quantitatively.
Index Terms: Denoising bounds, image clustering, image denoising, linear minimum mean-squared-error (LMMSE) estimator, Wiener filter.
324 .Accelerated Hypothesis Generation for Multistructure Data via Preference Analysis.
Abstract: Random hypothesis generation is integral to many robust geometric model fitting techniques. Unfortunately, it is also computationally expensive, especially for higher order geometric models and heavily contaminated data. We propose a fundamentally new approach to accelerate hypothesis sampling by guiding it with information derived from residual sorting. We show that residual sorting innately encodes the probability of two points having arisen from the same model, and is obtained without recourse to domain knowledge (e.g., keypoint matching scores) typically used in previous sampling enhancement methods. More crucially, our approach encourages sampling within coherent structures and thus can very rapidly generate all-inlier minimal subsets that maximize the robust criterion. Sampling within coherent structures also affords a natural ability to handle multistructure data, a condition that is usually detrimental to other methods. The result is a sampling scheme that offers substantial speed-ups on common computer vision tasks such as homography and fundamental matrix estimation. We show on many computer vision data, especially those with multiple structures, that ours is the only method capable of retrieving satisfactory results within realistic time budgets.
Index Terms: Geometric model fitting, robust estimation, hypothesis generation, residual sorting, multiple structures.
325. BM3D Frames and Variational Image Deblurring.
Abstract: A family of the block matching 3-D (BM3D) algorithms for various imaging problems has been recently proposed within the framework of nonlocal patchwise image modeling , . In this paper, we construct analysis and synthesis frames, formalizing BM3D image modeling, and use these frames to develop novel iterative deblurring algorithms. We consider two different formulations of the deblurring problem, i.e., one given by the minimization of the single-objective function and another based on the generalized Nash equilibrium (GNE) balance
of two objective functions. The latter results in the algorithm where deblurring and denoising operations are decoupled. The convergence of the developed algorithms is proved. Simulation
experiments show that the decoupled algorithm derived from the GNE formulation demonstrates the best numerical and visual results and shows superiority with respect to the state of the art in the field, confirming a valuable potential of BM3D-frames as an advanced image modeling tool.
Index Terms: Deblurring, frames, image modeling, image reconstruction, sparse representations.
326. Re-Initialization Free Level Set Evolution Via Reaction Diffusion
Abstract: This paper presents a novel reaction-diffusion (RD) method for implicit active contours, which is completely free of the costly re-initialization procedure in level set evolution (LSE). A diffusion term is introduced into LSE, resulting in a RD-LSE equation, to which a piecewise constant solution can be derived. In order to have a stable numerical solution of the RD based LSE, we propose a two-step splitting method (TSSM) to iteratively solve the RD-LSE equation: first iterating the LSE equation, and then solving the diffusion equation. The second step regularizes the level set function obtained in the first step to ensure stability, and thus the complex and costly re-initialization procedure is completely eliminated from LSE. By successfully applying diffusion to LSE, the RD-LSE model is stable by means of the simple finite difference method, which is very easy to implement. The proposed RD method can be generalized to solve the LSE for both variational level set method and PDE-based level set method. The RD-LSE method shows very good performance on boundary anti-leakage, and it can be readily extended to high dimensional level set method. The extensive and promising experimental results on synthetic and real images validate the effectiveness of the proposed RD-LSE approach.
Index Terms: Level set, reaction-diffusion, active contours, image segmentation, PDE, variational method
327. Monogenic Binary Coding: An Efficient Local Feature Extraction Approach To Face Recognition
Abstract: Local feature based face recognition (FR) methods, such as Gabor features encoded by local binary pattern, could achieve state-of-the-art FR results in large-scale face databases such as FERET and FRGC. However, the time and space complexity of Gabor transformation are too high for many practical FR applications. In this paper, we propose a new and efficient local feature extraction scheme, namely monogenic binary coding (MBC), for face representation and recognition. Monogenic signal representation decomposes an original signal into three complementary components: amplitude, orientation and phase. We encode the monogenic variation in each local region and monogenic feature in each pixel, and then calculatebthe statistical features (e.g., histogram) of the extracted local features. The local statistical features extracted from the complementary monogenic components (i.e., amplitude, orientation and phase) are then fused for effective FR. It is shown that the proposed MBC scheme has significantly lower time and space complexity than the Gabor-transformation based local feature methods. The extensive FR experiments on four large scale databases demonstrated the effectiveness of MBC, whose performance is competitive with and even better than state-of-the-art local feature based FR methods.
Keywords: monogenic signal analysis, monogenic binary coding, face recognition, LBP, Gabor filtering
328. Monotonic Regression: A New Way For Correlating Subjective And Objective Ratings In Image Quality Research
Abstract: To assess the performance of image quality metrics (IQMs), some regressions, such as logistic regression and polynomial regression, are used to correlate objective ratings with subjective scores. However, some defects in optimality are shown in these regressions. In this correspondence, monotonic regression (MR) is found to be an effective correlation method in the performance assessment of IQMs. Both theoretical analysis and experimental results have proven that MR performs better than any other regression. We believe that MR could be an effective tool for performance assessment in the IQM research.
Index Terms: Image quality assessment, image quality metric (IQM), metric performance, monotonic regression (MR).
329. Demonstration Of Real-Time Spectrum Sensing For Cognitive Radio
Abstract: Spectrum sensing detects the availability of the radio frequency spectrum in a real-time fashion, which is essential and vital to cognitive radio. The requirement for real-time processing indeed poses challenges on implementing spectrum sensing algorithms. Trade-off between the complexity and the effectiveness of spectrum sensing algorithms should be taken into consideration. In this paper, a fast Fourier transform (FFT) based spectrum sensing algorithm called FAR is introduced. It is the beauty of the algorithm that the decision variable is insensitive to noise level. Parameter selection for the algorithm is considered as well, toward minimizing computational complexity. A small form factor (SFF) software defined radio (SDR) development platform (DP) is employed to implement a spectrum sensing receiver with FAR algorithm. Performance of FAR algorithm is evaluated on the SFF SDR DP, and real-time spectrum sensing is demonstrated. FAR algorithm is friendly to hardware implementation and it is effective to detect signals at low SNR.
330. ML Estimation Of Time And Frequency Offset In OFDM Systems
Abstract: We present the joint maximum likelihood (ML) symbol-time and carrier-frequency offset estimator in orthogonal frequency-division multiplexing (OFDM) systems. Redundant information contained within the cyclic prefix enables this estimation without additional pilots. Simulations show that the frequency estimator may be used in a tracking mode and the time estimator in an acquisition mode.
331. Efficient Encoding Of Low-Density Parity-Check Codes
Abstract: Low-density parity-check (LDPC) codes can be considered serious competitors to turbo codes in terms of performance and complexity and they are based on a similar philosophy: constrained random code ensembles and iterative decoding algorithms. In this paper, we consider the encoding problem for LDPC codes. More generally, we consider the encoding problem for codes specified by sparse parity-check matrices. We show how to exploit the sparseness of the parity-check matrix to obtain efficient encoders. For the (3 6)-regular LDPC code, for example, the complexity of encoding is essentially quadratic in the block length. However, we show that the associated coefficient can be made quite small, so that encoding codes even of length 100 000 is still quite practical. More importantly, we will show that “optimized” codes actually admit linear time encoding.
Index Terms: Binary erasure channel, decoding, encoding, parity check, random graphs, sparse matrices, turbo codes.
332. Multi-User Diversity Vs. Accurate Channel State Information In MIMO Downlink
Abstract: In a multiple transmit antenna, single antenna per receiver downlink channel with limited channel state feedback, we consider the following question: given a constraint on the total system-wide feedback load, is it preferable to get low-rate/coarse channel feedback from a large number of receivers or high-rate/high-quality feedback from a smaller number of receivers? Acquiring feedback from many receivers allows multi-user diversity to be exploited, while high-rate feedback allows for very precise selection of beam forming directions. We show that there is a strong preference for obtaining high-quality feedback, and that obtaining near-perfect channel information from as many receivers as possible provides a significantly larger sum rate than collecting a few feedback bits from a large number of users.
333. Sum Power Iterative Water-Filling For Multi-Antenna Gaussian Broadcast Channels
Abstract: In this correspondence, we consider the problem of maximizing sum rate of a multiple-antenna Gaussian broadcast channel (BC). It was recently found that dirty-paper coding is capacity achieving for this channel. In order to achieve capacity, the optimal transmission policy (i.e., the optimal transmit covariance structure) given the channel conditions and power constraint must be found. However, obtaining the optimal transmission policy when employing dirty-paper coding is a computationally complex non convex problem. We use duality to transform this problem into a well-structured convex multiple-access channel (MAC) problem. We exploit the structure of this problem and derive simple and fast iterative algorithms that provide the optimum transmission policies for the MAC, which can easily be mapped to the optimal BC policies.
Index Terms: Broadcast channel, dirty-paper coding, duality, multipleaccess channel (MAC), multiple-input multiple-output (MIMO), systems.
334. On Optimal Power Control For Delay-Constrained Communication Over Fading Channels
Abstract: In this paper, we study the problem of optimal power control for delay-constrained communication over fading channels. Our objective is to find a power control law that optimizes the link layer performance, specifically, minimizes delay bound violation probability (or equivalently, the packet drop probability), subject to constraints on average power, arrival rate, and delay bound. The transmission buffer size is assumed to be finite; hence, when the buffer is full, there will be packet drop. The fading channel under our study has a continuous state, e.g., Rayleigh fading. Since directly solving the power control problem (which optimizes the link layer performance) is particularly challenging, we decompose it into three sub problems, and solve the three sub-problems iteratively; we call the resulting scheme Joint Queue Length Aware (JQLA) power control, which produces a local optimal solution to the three sub problems. We prove that the solution that simultaneously solves the three sub-problems is also an optimal solution to the optimal power control problem. Simulation results show that the JQLA scheme achieves superior performance over the time domain water filling and the truncated channel inversion power control. E.g., JQLA achieves 10 dB gain at packet drop probability of 10¡3, over the time domain water filling power control.
Index Terms: Delay-constrained communication, power control, queuing analysis, delay bound violation probability, packet drop probability.
336. An Improved Algorithm For Blind Reverberation Time Estimation
Abstract: An improved algorithm for the estimation of the reverberation time (RT) from reverberant speech signals is presented. This blind estimation of the RT is based on a simple statistical model for the sound decay such that the RT can be estimated by means of a maximum-likelihood (ML) estimator. The proposed algorithm has a significantly lower computational complexity than previous ML-based algorithms for RT estimation. This is achieved by a down sampling operation and a simple pre-selection of possible sound decays. The new algorithm is more suitable to track time-varying RTs than related approaches. In addition, it can also estimate the RT in the presence of (moderate) background noise. The proposed algorithm can be employed to measure the RT of rooms from sound recordings without using a dedicated measurement setup. Another possible application is its use within speech de reverberation systems for hands-free devices or digital hearing aids.
Index Terms: reverberation time, blind estimation, low complexity, speech dereverberation
337. Fast And Accurate Sequential Floating Forward Feature Selection With the Bayes Classifier Applied To Speech Emotion Recognition
Abstract: This paper addresses subset feature selection performed by the sequential floating forward selection (SFFS). The criterion employed in SFFS is the correct classification rate of the Bayes classifier assuming that the features obey the multivariate Gaussian distribution. A theoretical analysis that models the number of correctly classified utterances as a hyper geometric random variable enables the derivation of an accurate estimate of the variance of the correct classification rate during cross-validation. By employing such variance estimate, we propose a fast SFFS variant. Experimental findings on Danish emotional speech (DES) and Speech Under Simulated and Actual Stress (SUSAS) databases demonstrate that SFFS computational time is reduced by 50% and the correct classification rate for classifying speech into emotional states for the selected subset of features varies less than the correct classification rate found by the standard SFFS. Although the proposed SFFS variant is tested in the framework of speech emotion recognition, the theoretical results are valid for any classifier in the context of any wrapper algorithm.
Key words: Bayes classifier, cross-validation, variance of the correct classification rate of the Bayes classifier, feature selection, wrappers
338. Hybrid De Algorithm With Adaptive Crossover Operator For Solving Real-World Numerical Optimization Problems
Abstract: In this paper, the results for the CEC 2011 Competition on testing evolutionary algorithms on real world optimization problems using a hybrid differential evolution algorithm are presented. The proposal uses a local search routine to improve convergence and an adaptive crossover operator. According to the obtained results, this algorithm shows to be able to find competitive solutions with reported results.
Index Terms: Differential Evolution algorithm, parameter selection, CEC competition.
339. Real-Time Compressive Tracking
Abstract: It is a challenging task to develop effective and efficient appearance models for robust object tracking due to factors such as pose variation, illumination change, occlusion, and motion blur. Existing online tracking algorithms often update models with samples from observations in recent frames. While much success has been demonstrated, numerous issues remain to be addressed. First, while these adaptive appearance models are data-dependent, there does not exist sufficient amount of data for online algorithms to learn at the outset. Second, online tracking algorithms often encounter the drift problems. As a result of self-taught learning, these mis-aligned samples are likely to be added and degrade the appearance models. In this paper, we propose a simple yet effective and efficient tracking algorithm with an appearance model based on features extracted from the multi-scale image feature space with data-independent basis. Our appearance model employs nonadaptive random projections that preserve the structure of the image feature space of objects. A very sparse measurement matrix is adopted to efficiently extract the features for the appearance model. We compress samples of foreground targets and the background using the same sparse measurement matrix. The tracking task is formulated as a binary classification via a naive Bayes classifier with online update in the compressed domain. The proposed compressive tracking algorithm runs in real-time and performs favorably against state-of-the-art algorithms on challenging sequences in terms of efficiency, accuracy and robustness.
340. An Efficient Algorithm For Level Set Method Preserving Distance Function
Abstract: The level set method is a popular technique for tracking moving interfaces in several disciplines including computer vision and fluid dynamics. However, despite its high flexibility, the original level set method is limited by two important numerical issues. Firstly, the level set method does not implicitly preserve the level set function as a distance function, which is necessary to estimate accurately geometric features s.a. the curvature or the contour normal. Secondly, the level set algorithm is slow because the time step is limited by the standard CFL condition, which is also essential to the numerical stability of the iterative scheme. Recent advances with graph cut methods and continuous convex relaxation provide powerful alternatives to the level set method for image processing problems because they are fast, accurate and guaranteed to find the global minimizer independently to the initialization. These recent techniques use binary functions to represent the contour rather than distance functions, which are usually considered for the level set method. However, the binary function cannot provide the distance information, which can be essential for some applications s.a. the surface reconstruction problem from scattered points and the cortex segmentation problem in medical imaging. In this paper, we propose a fast algorithm to preserve distance functions in level set methods. Our algorithm is inspired by recent efficient `1 optimization techniques, which will provide an efficient and easy to implement algorithm. It is interesting to note that our algorithm is not limited by the CFL condition and it naturally preserves the level set function as a distance function during the evolution, which avoids the classical re-distancing problem in level set methods. We apply the proposed algorithm to carry out image segmentation, where our methods proves to be 5 to 6 times faster than standard distance preserving level set techniques. We also present two applications where preserving a distance function is essential. Nonetheless, our method stays generic and can be applied to any level set methods that require the distance information.
Index Terms: Level set, image segmentation, surface reconstruction, signed distance function, numerical scheme, splitting.
341. Efficient Misalignment-Robust Representation For Real-Time Face Recognition
Abstract: Sparse representation techniques for robust face recognition have been widely studied in the past several years. Recently face recognition with simultaneous misalignment, occlusion and other variations has achieved interesting results via robust alignment by sparse representation (RASR). In RASR, the best alignment of a testing sample is sought subject by subject in the database. However, such an exhaustive search strategy can make the time complexity of RASR prohibitive in large-scale face databases. In this paper, we propose a novel scheme, namely misalignment robust representation (MRR), by representing the misaligned testing sample in the transformed face space spanned by all subjects. The MRR seeks the best alignment via a two-step optimization with a coarse-to-fine search strategy, which needs only two deformation-recovery operations. Extensive experiments on representative face databases show that MRR has almost the same accuracy as RASR in various face recognition and verification tasks but it runs tens to hundreds of times faster than RASR. The running time of MRR is less than 1 second in the large-scale Multi-PIE face database, demonstrating its great potential for real-time face recognition.
342. Robust Point Matching Revisited: A Concave Optimization Approach
Abstract: The well-known robust point matching (RPM) method uses deterministic annealing for optimization, and it has two problems. First, it cannot guarantee the global optimality of the solution and tends to align the centers of two point sets. Second, deformation needs to be regularized to avoid the generation of undesirable results. To address these problems, in this paper we show that the energy function of RPM can be reduced to a concave function with very few non-rigid terms after eliminating the transformation variables and applying linear transformation; we then propose to use concave optimization technique to minimize the resulting energy function. The proposed method scales well with problem size, achieves the globally optimal solution, and does not need regularization for simple transformations such as similarity transform. Experiments on synthetic and real data validate the advantages of our method in comparison with state-of-the-art methods.
343. Canny Edge Detection Enhancement By Scale Multiplication
344. Robust Object Tracking Using Joint Color-Texture Histogram
Abstract: A novel object tracking algorithm is presented in this paper by using the joint color texture histogram to represent a target and then applying it to the mean shift framework. Apart from the conventional color histogram features, the texture features of the object are also extracted by using the local binary pattern (LBP) technique to represent the object. The major uniform LBP patterns are exploited to form a mask for joint color-texture feature selection. Compared with the traditional color histogram based algorithms that use the whole target region for tracking, the proposed algorithm extracts effectively the edge and corner features in the target region, which characterize better and represent more robustly the target. The experimental results validate that the proposed method improves greatly the tracking accuracy and efficiency with fewer mean shift iterations than standard mean shift tracking. It can robustly track the target under complex scenes, such as similar target and background appearance, on which the traditional color based schemes may fail to track.
Keywords: Object tracking; mean shift; local binary pattern; color histogram.
345. Distance Regularized Level Set Evolution And Its Application To Image Segmentation
Abstract: Level set methods have been widely used in image processing and computer vision. In conventional level set formulations, the level set function typically develops irregularities during its evolution, which may cause numerical errors and eventually destroy the stability of the evolution. Therefore, a numerical remedy, called re initialization, is typically applied to periodically replace the degraded level set function with a signed distance function. However, the practice of re initialization not only raises serious problems as when and how it should be performed, but also affects numerical accuracy in an undesirable way. This paper proposes a new variational level set formulation in which the regularity of the level set function is intrinsically maintained during the level set evolution. The level set evolution is derived as the gradient flow that minimizes an energy functional with a distance regularization term and an external energy that drives the motion of the zero level set toward desired locations. The distance regularization term is defined with a potential function such that the derived level set evolution has a unique forward-and-backward (FAB) diffusion effect, which is able to maintain a desired shape of the level set function, particularly a signed distance profile near the zero level set. This yields a new type of level set evolution called distance regularized level set evolution (DRLSE). The distance regularization effect eliminates the need for reinitialization and thereby avoids its induced numerical errors. In contrast to complicated implementations of conventional level set formulations, a simpler and more efficient finite difference scheme can be used to implement the DRLSE formulation. DRLSE also allows the use of more general and efficient initialization of the level set function. In its numerical implementation, relatively large time steps can be used in the finite difference scheme to reduce the number of iterations, while ensuring sufficient numerical accuracy. To demonstrate the effectiveness of the DRLSE formulation, we apply it to an edge-based active contour model for image segmentation, and provide a simple narrowband implementation to greatly reduce computational cost.
Index Terms: Forward and backward diffusion, image segmentation, level set method, narrowband, reinitialization.
346. Minimization Of Region-Scalable Fitting Energy For Image Segmentation
Abstract: Intensity inhomogeneities often occur in real-world images and may cause considerable difficulties in image segmentation. In order to overcome the difficulties caused by intensity inhomogeneities, we propose a region-based active contour model that draws upon intensity information in local regions at a controllable scale. A data fitting energy is defined in terms of a contour and two fitting functions that locally approximate the image intensities on
the two sides of the contour. This energy is then incorporated into a variational level set formulation with a level set regularization term, from which a curve evolution equation is derived for energy minimization. Due to a kernel function in the data fitting term, intensity information in local regions is extracted to guide the motion of the contour, which thereby enables our model to cope with intensity inhomogeneity. In addition, the regularity of the level set function is intrinsically preserved by the level set regularization term to ensure accurate computation and avoids expensive reinitialization of the evolving level set function. Experimental results for synthetic and real images show desirable performances of our method.
Index Terms: Image segmentation, intensity inhomogeneity, level set method, region-scalable fitting energy, variational method.
347. Motion Tracking
Abstract: The motion tracking task was decomposed into two independent subproblems. The _rst is to detect foreground objects on a frame-wise basis, by labelling each pixel in an image frame as either foreground or background. The second is to couple object observations at di_erent points in a sequence to yield the object’s motion trajectory.
348. A Level Set Method For Image Segmentation In The Presence Of Intensity In homogeneities With Application To MRI
Abstract: Intensity inhomogeneity often occurs in real-world images, which presents a considerable challenge in image segmentation. The most widely used image segmentation algorithms are region-based and typically rely on the homogeneity of the image intensities in the regions of interest, which often fail to provide accurate segmentation results due to the intensity inhomogeneity. This paper proposes a novel region-based method for image segmentation, which is able to deal with intensity inhomogeneities in the segmentation. First, based on the model of images with intensity inhomogeneities, we derive a local intensity clustering property of the image intensities, and define a local clustering criterion function for the image intensities in a neighborhood of each point. This local clustering criterion function is then integrated with respect to the neighborhood center to give a global criterion of image segmentation. In a level set formulation, this criterion defines an energy in terms of the level set functions that represent a partition of the image domain and a bias field that accounts for the intensity inhomogeneity of the image. Therefore, by minimizing this energy, our method is able to simultaneously segment the image and estimate the bias field, and the estimated bias field can be used for intensity inhomogeneity correction (or bias correction). Our method has been validated on synthetic images and real images of various modalities, with desirable performance in the presence of intensity inhomogeneities. Experiments show that our method is more robust to initialization, faster and more accurate than the well-known piecewise smooth model. As an application, our method has been used for segmentation and bias correction of magnetic resonance (MR) images with promising results.
Index Terms: Bias correction, image segmentation, intensity inhomogeneity, level set, MRI.
1. An Image Steganography Technique using X-Box Mapping
Abstract: Image Steganography is a method of concealing information into a cover image to hide it.
Least Significant-Bit (LSB) based approach is most popular steganographic techniques in spatial domain due to its simplicity and hiding capacity. This paper presents a novel technique for Image Steganography based on LSB using X-box mapping where we have used several Xboxes having unique data. The embedding part is done by this Steganography algorithm where we use four unique X-boxes with sixteen different values (represented by 4- bits) and each value is mapped to the four LSBs of the cover image. This mapping provides sufficient security to the payload because without knowing the mapping rules
no one can extract the secret data (payload).
2. FPGA Implementation of high speed 8-bit Vedic multiplier using barrel shifter
Abstract– This paper describes the implementation of an 8-bit Vedic multiplier enhanced in terms of propagation delay when compared with conventional multiplier like array multiplier, Braun multiplier, modified booth multiplier and Wallace tree multiplier. In our design we have utilized 8-bit barrel shifter which requires only one clock cycle for ‘n’ number of shifts. The design is implemented and verified using FPGA and ISE Simulator. The core was implemented on Xilinx Spartan-6 family xc6s1x75T-3-fgg676 FPGA. The propagation delay comparison was extracted from the synthesis report and static timing report as well. The design could achieve propagation delay of 6.781ns using barrel shifter in base selection module and multiplier
3. Design of Low Power TPG Using LP-LFSR
Abstract- This paper presents a novel test pattern generator which is more suitable for built in self test (BIST) structures used for testing of VLSI circuits. The objective of the BIST is to reduce power dissipation without affecting the fault coverage. The proposed test pattern generator reduces the switching activity among the test patterns at the most. In this approach, the single input change patterns generated by a counter and a gray code generator are Exclusive–ORed with the seed generated by the low power linear feedback shift register [LP-LFSR]. The proposed scheme is evaluated by using, a synchronous pipelined 4×4 and 8×8 Braun array multipliers. The System-On-Chip (SOC) approach is adopted for implementation on Altera Field Programmable Gate Arrays (FPGAs) based SOC kits with Nios II soft-core processor. From the implementation results, it is verified that the testing power for the proposed method is reduced by a significant percentage.
4. An Implementation of AES Algorithm Based on FPGA
Abstract—An implementation of high speed AES algorithm based on FPGA is presented in this paper in order to improve the safety of data in transmission. The mathematic principle, encryption process and logic structure of AES algorithm are introduced. So as to reach the purpose of improving the system computing speed, the pipelining and parallel processing methods were used. The simulation results show that the high-speed AES encryption algorithm implemented correctly. Using the method of AES encryption the data could be protected effectively.
5. Speed optimization of a FPGA based modified Viterbi Decoder
Abstract — In the modern era of electronics and communication decoding and encoding of any data(s) using VLSI technology requires low power, less area and high speed constrains. The viterbi decoder using survivor path with necessary parameters for wireless communication is an attempt to reduce the power and cost and at the same time increase the speed compared to normal decoder. This paper presents three objectives. Firstly, an orthodox viterbi decoder is designed and simulated. For faster process application, the Gate Diffused Input Logic (GDIL) based viterbi decoder is designed using Xilinx ISE, simulated and synthesized successfully. The new proposed GDIL viterbi provides very less path delay with low power simulation results. Secondly, the GDIL viterbi is again compared with our proposed technique, which comprises a Survivor Path Unit (SPU) implements a trace back method with DRAM. This proposed approach of incorporating DRAM stores the path information in a manner which allows fast read access without requiring physical partitioning of the DRAM. This leads to a comprehensive gain in speed with low power effects. Thirdly, all the viterbi decoders are compared, simulated, synthesized and the proposed approach shows the best simulation and synthesize results for low power and high speed application in VLSI design. The Add-Compare-Select (ACS) and Trace Back (TB) units and its sub circuits of the decoder(s) have been operated in deep pipelined manner to achieve high transmission rate. Although the register exchange based survivor unit has better throughput when compared to trace back unit, but in this paper by introducing the RAM cell between the ACS array and output register bank, a significant amount of reduction in path delay has been observed. All the designing of viterbi is done using Xilinx ISE 12.4 and synthesized successfully in the FPGA Spartan-3 target device operated at 64.516 MHz clock frequency, reduces almost 41% of total path delay.
6. Traffic-aware Design of a High Speed FPGA Network Intrusion Detection System
Abstract—Security of today’s networks heavily rely on Network Intrusion Detection Systems (NIDSs). The ability to promptly update the supported rule sets and detect new emerging attacks makes Field Programmable Gate Arrays (FPGAs) a very appealing technology. An important issue is how to scale FPGA-based NIDS implementations to ever faster network links. Whereas a trivial approach is to balance traffic over multiple, but functionally equivalent, hardware blocks, each implementing the whole rule set (several thousands rules), the obvious cons is the linear increase in the resource occupation. In this work, we promote a different, traffic-aware, modular approach in the design of FPGA-based NIDS. Instead of purely splitting traffic across equivalent modules, we classify and group homogeneous traffic, and dispatch it to differently capable hardware blocks, each supporting a (smaller) rule set tailored to the specific traffic category. We implement and validate our approach using the rule set of the well known Snort NIDS, and we experimentally investigate the emerging trade-offs and advantages, showing resource savings up to 80% based on real world traffic statistics gathered from an operator’s backbone.
7. Design and Implementation of Automated Wave-Pipelined Circuit using ASIC
Abstract— Wave-pipelining enables a digital circuit to be operated at higher frequency. In the literature, only trial and error and manual procedures are adopted for the choice of the optimum value of clock and clock skew between the I/O registers of wave-pipelined circuits. The major contribution of this paper is the proposal for automating the above procedure for the ASIC implementation of wave-pipelined circuits using built in self test approach. This is studied by a multiplier using dedicated AND gate by adopting three different schemes: wave-pipelining, pipelining and non-pipelining. From the implementation results, it is verified that the wavepipelined multipliers are faster by a factor of 1.08 compared to the non-pipelined multipliers. The wavepipelined Multiplier dissipates less power in the factor of 1.43 compared to the pipelined multiplier.
8. FPGA-based adaptive noise cancellation for ultrasonic NDE application
Abstract— Adaptive filter has been widely used in different applications for interference cancellation, predication, inverse modeling and identifications. In this paper, Field Programmable Gate Array (FPGA)-based adaptive noise cancellation is studied for adaptive filtering in ultrasonic non-destructive evaluation. Simulation and experimental results showed that backscattered noise from microstructures inside material can be efficiently reduced by adaptive filter. Additionally, four different architectures of filter realization on FPGA are discussed and compared. This type of study could have a broad range of applications such as target detection, object localization and pattern recognition.
9. FPGA Based Implementation of a Double Precision IEEE Floating-Point Adder
Abstract-Floating-Point addition imposes a great challenge during implementation of complex algorithm in hard realtime due to the enormous computational burden associated with repeated calculations with high precision numbers. Moreover, at the hardware level, any basic addition or subtraction circuit has to incorporate the alignment of the significands. This paper presents a novel technique to implement a double precision IEEE floating-point adder that can complete the operation within two clock cycles. The proposed technique has exhibited improvement in the latency and also in the operational chip area management. The proposed double precision IEEE floating-point adder has been implemented with XC2V6000 and XC3SI500 Xilinx© FPGA devices.
10. Least Complex S-Box and Its Fault Detection for Robust Advanced Encryption Standard Algorithm
Abstract– Advanced Encryption Standard (AES) is the symmetric key standard for encryption and decryption. In this work, a 128-bit AES encryption and decryption using Rijndael Algorithm is designed and synthesized using verilog code. The fault detection scheme for their hardware implementation plays an important role in making the AES robust to the internal and malicious faults. In the proposed AES, a composite field S-Box and inverse S-Box is implemented using logic gates and divided them into five blocks. Any natural or malicious faults which defect the logic gates are detected using parity based fault detection scheme. For increasing the fault exposure, the predicted parities of each of the block S-box and inverse S-box are obtained. The multi-bit parity prediction approach has low cost and high error coverage than the approaches using single bit parities. The Field Programmable Gate Array (FPGA) implementation of the fault detection structure has better hardware and time complexities.
11. An Application Instance of FPGA in the Field of PHM
Abstract-With the extensive application of new types of sensors, the rate of data acquisition and transmission are becoming a problem in Prognostic and Health Management (PHM). This paper presents an FPGA-based method for high speed data acquisition and transmission taking full advantage of the parallel processing capabilities and easy to modify and upgrade features of FPGA, to cope with the difficulties of highspeed data acquisition and transmission. This article focuses on the components performance and characteristics of the FPGA based fault prediction and diagnosis system. The system uses an FPGA chip as the core operational component to achieve fast transfer of large amounts of data by FIFO. The use of programmable FPGA hardware, makes the data acquisition system design flexible, while improving the reliability of the system. It is also important for achieving the real-time online monitoring of failure.
12. A Moving Window Architecture for a HW/SW Codesign Based Canny Edge Detection for FPGA
Abstract – This paper proposes an accelerator for Canny edge detection implemented on FPGA. The proposed architecture relies on a moving window consisting of 7×8 pixels, which performs the more computational complex operations of the algorithm: smoothing, gradient’s magnitude and direction computation, nonmaximum suppression and double thresholding. By employing the proposed window, intermediate results are stored within the FPGA, without the need to buffer them in large memory structures. Furthermore, the design has a high throughput rate, due to its large numbers of pipeline stages, allowing considerable performance for the proposed algorithm.
13. An Electrocardiogram Diagnostic System Implemented in FPGA
Abstract—In this paper, we present a signal processing method capable of detecting angina in electrocardiograms, and its implementation in Field Programmable Gate Array – FPGA. The adopted procedure is based on fuzzy clustering to reduce the amount of data sampling and a comparison with samples from a previously established database. By using the correlation method on the samples, it is possible to establish an initial indication of angina. The reduced number of samples of the clustering process turns the processing simpler and allows its hardware (FPGA) implementation. According to the tests conducted, the method achieves 85% correct diagnoses.
14. Enhanced Area Effi cient Architecture for 128 bit Modified CSLA
Abstract– In the design of Integrated circuits, area occupancy plays a vital role because of increasing necessity of portable systems. Carry Select Adder (CSLA) is a fast adder used in dataprocessing processors for performing fast arithmetic functions. From the structure of the CSLA, the scope is to reduce the area of CSLA based on the efficient gate-level modification. In this paper 128 bit Regular Linear CSLA, Modified Linear CSLA, Regular Square-root CSLA (SQRT CSLA) and Modified SQRT CSLA architectures have been developed and compared. However, the Regular CSLA is still area-consuming due to the dual RippleCarry Adder (RCA) structure. For reducing area, the CSLA can be implemented by using a single RCA and an add-one circuit instead of using dual RCA. Comparing the Regular Linear CSLA with Regular SQRT CSLA, the Regular SQRT CSLA has reduced area as well as comparing the Modified Linear CSLA with Modified SQRT CSLA; the Modified SQRT CSLA has reduced area. The results and analysis show that the Modified Linear CSLA and Modified SQRT CSLA provide better outcomes than the Regular Linear CSLA and Regular SQRT CSLA respectively. This project was aimed for implementing high performance optimized FPGA architecture. Modelsim 6.3c is used for simulating the CSLA and synthesized using Xilinx PlanAhead12.2. Then the implementation is done in spartan3 FPGA Kit.
15. PNOC: Implementation on Verilog for FPGA
Abstract—Network on Chip (NoC) architectures provide a very efficient means for performance enhancement in digital circuits. The paper describes a NoC implementation that is specifically targeted towards FPGA based designs. Our implementation is based on a lightweight circuit-switched architecture called programmable NoC (PNoC). It is captured in the Verilog hardware description language and is implemented using the Xilinx Virtex-II pro FPGA (XC2Vp30-7) device at 126 MHz. The proposed architecture allows parametrization at the compile time for the number of nodes and amount of data. Moreover, experimental results have confirmed that the proposed implementation is the most efficient one in terms of performance.
16. Real-time FPGA-based Template Matching Module for Visual Inspection Application
Abstract-Template matching enables localization of objects under inspection, but suffers from long computation due to high computation complexity. In this work, a real-time FPGA-based template matching module which accelerates time consuming normalized cross-correlation (NCC) template matching was presented. To improve NCC computation speed, we simplified the original NCC algorithm and designed pipelined parallel processing circuit architecture. Experimental results showed that our FPGA module accelerates NCC speed up to 80 times faster than PC performance. The real-time template matching module has been integrated into an LED die inspection system to localize LED dies. This real-time template matching module can be applied to LED, PV, and semiconductor inspection and manufacturing applications. Furthermore, this module can also be applied to vision applications for either service or industrial robots.
17. High-performance Implementation of a New Hash Function on FPGA
Abstract— Skein has the advantages of higher security (resisting against traditional attacks), faster speed and selectable parameters. Therefore, it becomes a strong competitor for next generation secure hash algorithm standard (SHA-3) which will be used widely in communication and security for substitution of SHA-2. The problems of existing works lie in implementation for only one structure and lack detailed comparison of different structures. Based on analysis of the algorithm, we accomplished three structures (iterative, 4-unrolled and 8-unrolled) of Skein and ported the designs to FPGA respectively. Finally detailed analysis and comparison with our different structures and other implementations are provided from aspects of hardware resource and performance. The results show that our implementation has better performance and takes up less hardware resources than existing works under the same structure. Our implementation can meet the requirement of real-time and high performance field.
18. Improved Floating-Point Matrix Multiplier
Abstract – Floating-point matrix multiplier is widely used in scientific computations. A great deal of efforts has been made to achieve higher performance. The matrix multiplication consists of many multiplications and accumulations. Yang and Duh proposed a modular design of floating-point matrix multiplier which reserving intermediate result as two vectors. It brings shorter delay but more cost. This work modifies Yang and Duh’s design with Booth encoding in multiplication to reduce the number of partial products. As the result, the improved floating-point matrix multiplier has better performance with shorter delay and much less hardware cost than Yang and Duh’s design.
19. An area efficient multiplexer based CORDIC
Abstract—In the literature, multiplexer has been proposed for the ASIC implementation of unrolled CORDIC (Coordinate Rotation DIgital Computer) processor. In this paper, the efficacy of this approach is studied for the implementation on FPGA. For this study, both non pipelined and 2 level pipelined CORDIC with 8 stages and using two schemes – one using adders in all the stages and another using multiplexers in the second and third stages. A 16 bit CORDIC for generating the sine/cosine functions is implemented using all the four schemes on both Xilinx Virtex 6 FPGA(XC6VLX240) and Altera Cyclone II FPGA(EP2C20F484C7). From the implementation results, it is found that the nonpipelined and pipelined CORDICs using multiplexer requires 1.6, 1.4 times lower area in Xilinx FPGA and 1.8, 1.6 times lower area in Altera FPGA than that using only adders. This is achieved without reduction in speed.
20. Simulation and Implementation of LDPC Code in FPGA
Abstract—The paper deals with implementation of Low-Density Parity-Check (LDPC) codes  in FPGA-based bridge for Free- Space Optical link. The coder was designed with a regular parity matrix for code rate 1/2. The matrix of dimension 8×16 for the experimental implementation was found using a random search in MATLAB. The main advantage of this matrix is the decoder can correct all single-bit errors. The simulation for all possible values shows that Bit Error Ratio (BER) is zero. This result was not obtained with other matrices. An experimental communication channel was realized with encoder and decoder implemented in FPGA Virtex 5 development board ML505. DIP switches are sources for information bits and these values are shown on LCD display. The bit-flipping method is used in decoder and result code word is shown in the second line on the LCD display.
21.FPGA based implementation of a fuzzy Neural network modular architecture For embedded systems
This paper presents a FPGA based approach for a modular architecture of Fuzzy Neural Networks (FNN) to embed easily different topologies set up. The project is based on a Takagi – Hayashi (T-H) method for the construction and tuning of fuzzy rules, this is commonly referred as neural network driven fuzzy reasoning. The proposed architecture approach consists of two main configurable modules: a Multilayer Perceptron – MLP with sigmoidal activation function that composes the first module to determine a Fuzzy membership function; the second employs an MLP with pure linear activation function to define the consequents. The DSPBuilder® software along the Simulink® is used to connect, set and synthesize the Fuzzy Neural Network desired. Other hardware components employed in the architecture proposed cooperate to the system modularity. The system was tested and validated through a control problem and an interpolation problem. Several papers proposed different hardware architecture to implement hybrid systems by using Fuzzy logic and Neural Network. However, there is no approach with this specific neural network driven fuzzy reasoning by T-H method and the aim to be embedded. The Self-Organizing Map (SOM) and Levenberg-Marquardt back propagation were used to train the FNN proposed off-line.
22. Efficient Interleaver Design for MIMO-OFDM Based Communication Systems on FPGA
In this paper, we present a memory-efficient and faster interleaver implementation technique for MIMO-OFDM communication systems on FPGA. The IEEE 802.16 standard is used as a reference for simulation, implementation, and analysis. A method for the interleaver design on FPGA and its memory utilization results are presented. Our design utilizes the minimum required on-chip memory for the interleaver implementation. Using the proposed interleaver design method, the data rates for MIMO-OFDM based communication systems are doubled for 2×2 MIMO systems without using the transmit diversity.
23. A FPGA-Based Deep Packet Inspection Engine for Network Intrusion Detection System
Abstract— Pattern matching has became a bottleneck of software based Network Intrusion Detection System (NIDS) as the number of signature have recently increased dramatically. Many FPGA based architectures for detecting malicious patterns have been proposed recently. However, these approaches have just considered matching pattern separately while more and more complex combination of several patterns are utilized to describe intrusion activities. In this paper we present our work which concentrates on multi-pattern signature and propose a FPGA based deep packet inspection engine for NIDS. The system can support both static and dynamic patterns. We employ Snort signature set and realize our system on Net FPGA platform. The evaluation on real network environment shows that our system can maintain gigabit line rate throughput without dropping packets.
24. FPGA Implementation of 16-Point Radix-4 Complex FFT Core Using NEDA
Abstract–NEDA is one of the techniques to implement many digital signal processing systems that require multiply and accumulate units. FFT is one of the most employed blocks in many communication and signal processing systems. This paper proposes FPGA implementation of a 16 point radix-4 complexFFT core using NEDA. The proposed design has improvement in terms of hardware utilization compared to traditional methods. The design has been implemented on a range of FPGAs to compare the performance. The proposed design has a power consumption of 728.89 mW on XC2VP100-6FF1704 FPGA at 50 MHz. The maximum frequency achieved is 114.27 MHz on XC5VLX330-2FF1760 FPGA at a cost of higher power and the maximum throughput observed is 1828.32 Mbit/s and minimum slice delay product observed is 9.18. The design is also implemented using synopsys DC synthesis for both 65 nm and 180 nm technology libraries.
25. A High-Performance FPGA-Based Implementation of the LZSS Compression Algorithm
The increasing growth of embedded networking applications has created a demand for high-performance logging systems capable of storing huge amounts of high-bandwidth, typically redundant data. An efficient way of maximizing the logger performance is doing a real-time compression of the logged stream. In this paper we present a flexible high-performance implementation of the LZSS compression algorithm capable of processing up to 50 MB/s on a Virtex-5 FPGA chip. We exploit the independently addressable dual-port block RAMs inside the FPGA chip to achieve an average performance of 2 clock cycles per byte. To make the compressed stream compatible with the ZLib library  we encode the LZSS algorithm output using a fixed Huffman table defined by the Deflate specification . We also demonstrate how changing the amount of memory allocated to various internal tables impacts the performance and compression ratio. Finally, we provide a cycle-accurate estimation tool that allows finding a trade-off between FPGA resource utilization, compression ratio and performance for a specific data sample.
26. FPGA Implementation of heterogeneous multicore platform with SMID/MIMD custom accelerators
27. Novel High Speed Vedic Mathematics Multiplie using Compressors
Abstract—With the advent of new technology in the fields of VLSI and communication, there is also an ever growing demand for high speed processing and low area design. It is also a well known fact that the multiplier unit forms an integral part of processor design. Due to this regard, high speed multiplier architectures become the need of the day. In this paper, we introduce a novel architecture to perform high speed multiplication using ancient Vedic maths techniques. A new high speed approach utilizing 4:2 compressors and novel 7:2 compressors for addition has also been incorporated in the same and has been explored. Upon comparison, the compressor based multiplier introduced in this paper, is almost two times faster than the popular methods of multiplication. With regards to area, a 1% reduction is seen. The design and experiments were carried out on a Xilinx Spartan 3e series of FPGA and the timing and area of the design, on the same have been calculated.
28. FPGA Implementation of BASK-BFSK-BPSK Digital Modulators
Abstract: Field-programmable gate-array (FPGA) implementations of binary amplitude-shift keying (BASK), binary frequency shift keying (BFSK), and binary phase-shift keying (BPSK) digital modulators are presented. The proposed designs are aimed at educational purposes in a digital communication course. They employ the minimum number of blocks necessary for achieving BASK, BFSK, and BPSK modulation, and for full integration with the other functional parts of the Altera Development and Education (DE2) FPGA board. The input carrier signal and the bit stream (modulating signal) are user controllable. These digital modulators were developed and compiled to a Verilog Hardware Description Language (HDL) netlist, and were later implemented into an Altera DE2 FPGA board. The functionality of these digital modulators was demonstrated through simulations using the Quartus II simulation software, and experimental measurements of the real-time modulated signal via an oscilloscope.
29. Design and Implementation of Adaptive filtering algorithm for Noise Cancellation in speech signal on FPGA
Abstract- In recent years FPGA systems are replacing dedicated Programmable Digital Signal Processor (PDSP) systems due to their greater flexibility and higher bandwidth, resulting from their parallel architecture. This paper presents the applicability of a FPGA system for speech processing. Here adaptive filtering technique is used for noise cancellation in speech signal. Least Mean Squares (LMS ) , one of the widely used algorithm in many signal processing environment , is implemented for adaption of the filter coefficients. The cancellation system is implemented in VHDL and tested for noise cancellation in speech signal. The simulation of VHDL design of adaptive filter is performed and analyzed on the basis of Signal to Noise ratio (SNR) and Mean Square Error (MSE).
30. A Programmable FPGA-based 8-Channel Arbitrary Waveform Generator for Medical Ultrasound Research Activities
Abstract: In modern ultrasound imaging systems, digital transmit beamformer module typically generates accurate control of the amplitude of individual elements in a multielement array probe, as well as of the time delays and phase between them, to enable the acoustic beam to be focused and/or steered electronically. However, these systems do not provide the ultrasound researchers access to transmit front-end module. This paper presents the development of a digital transmit beamformer system for generating simultaneous arbitrary waveforms, specifically designed for research purposes. The proposed architecture has 8 independent excitation channels and uses an FPGA (Field Programmable Gated Array) device for electronic steering and focusing of ultrasound beam. The system allows operation in pulse-echo mode, with pulse repetition rate of excitation from 62.5 Hz to 8 kHz, center frequency from 500 kHz to 20 MHz, excitation voltage over 100 Vpp, and individual control of amplitude apodization, phase angle and time delay trigger. Experimental results show that this technique is suitable for generating the excitation waveforms needed for medical ultrasound imaging researches.
31. Area-Time Efficient Scaling-Free CORDIC Using Generalized Micro-Rotation Selection
Abstract—This paper presents an area-time efficient CORDIC algorithm that completely eliminates the scale-factor. By suitable selection of the order of approximation of Taylor series the proposed CORDIC circuit meets the accuracy requirement, and attains the desired range of convergence. Besides we have proposed an algorithm to redefine the elementary angles for reducing the number of CORDIC iterations. A generalized micro-rotation selection technique based on high speed most-significant-1-detection obviates the complex search algorithms for identifying the micro-rotations. The proposed CORDIC processor provides the flexibility to manipulate the number of iterations depending on the accuracy, area and latency requirements. Compared to the existing recursive architectures the proposed one has 17% lower slice-delay product on Xilinx Spartan XC2S200E device.
32. ADPLL Design and Implementation on FPGA
Abstract:-This paper presents the ADPLL design using Verilog and its implementation on FPGA. ADPLL is designed using Verilog HDL. Xilinx ISE 10.1 Simulator is used for simulating Verilog Code.This paper gives details of the basic blocks of an ADPLL. In this paper, implementation of ADPLL is described in detail. Its simulation results using Xilinx are also discussed. It also presents the FPGA implementation of ADPLL design on Xilinx vertex5 xc5vlx110t chip and its results. The ADPLL is designed of 200 kHz central frequency. The operational frequency range of ADPLL is 189 Hz to 215 kHz, which is lock range of the design.
33. Implementation and Comparison of Effective Area Efficient Architectures for CSLA
Abstract– In the design of Integrated circuits, area occupancy plays a vital role because of increasing necessity of portable systems. Carry Select Adder (CSLA) is a fast adder used in data processing processors for performing fast arithmetic functions. From the structure of the CSLA, the scope is to reduce the area of CSLA based on the efficient gate-level modification. In this paper 128 bit Regular Linear CSLA, Modified Linear CSLA, Regular Square-root CSLA (SQRT CSLA) and Modified SQRT CSLA architectures have been developed and compared. However, the Regular CSLA is still area-consuming due to the dual RippleCarry Adder (RCA) structure. For reducing area, the CSLA can be implemented by using a single RCA and an add-one circuit instead of using dual RCA. Comparing the Regular Linear CSLA with Regular SQRT CSLA, the Regular SQRT CSLA has reduced area as well as comparing the Modified Linear CSLA with Modified SQRT CSLA; the Modified SQRT CSLA has reduced area. The results and analysis show that the Modified Linear CSLA and Modified SQRT CSLA provide better outcomes than the Regular Linear CSLA and Regular SQRT CSLA respectively. This project was aimed for implementing high performance optimized FPGA architecture. Modelsim 6.3c is used for simulating the CSLA and synthesized using Xilinx PlanAhead12.2. Then the implementation is done in spartan3 FPGA Kit.
34. Automatic Gain Control on FPGA for Software- Defined Radios
Abstract— This paper introduces an efficient implementation of the Automatic Gain Control (AGC) for an IEEE 802.15.3c compliant receiver developed using a Field-Programmable Gate Arrays (FPGAs), both feed-forward and feed-backward AGCs are designed, implemented and evaluated.
35. Design of Plural-Multiplier Based on CORDIC Algorithm for FFT Application
Abstract—CORDIC plural-multiplier is the key module to affecting the speed and accuracy of FFT processor. Considering these demands, the problem of CORDIC algorithm is discussed in detail and the according optimization methods are given in this paper. Then, the hardware pipelining structure of the CORDIC multiplier is put forward. Comparison results about RTL simulation results with MATLAB calculation indicate that the design is feasible and practical.
36. VLSI Friendly ECG QRS Complex Detector for Body Sensor Networks
Abstract—This paper aims to present a very-large-scale integration (VLSI) friendly electrocardiogram (ECG) QRS detector for body sensor networks. Baseline wandering and background noise are removed from original ECG signal by a mathematical morphological method. Then the multipixel modulus accumulation is employed to act as a low-pass filter to enhance the QRS complex and improve the signal-to-noise ratio. The performance of the algorithm is evaluated with standard MIT-BIH arrhythmia database and wearable exercise ECG Data. Corresponding power and area efficient VLSI architecture is designed and implemented on a commercial nano-FPGA. High detection rate and high speed demonstrate the effectiveness of the proposed detector.
37. FPGA Architecture for OFDM Software Defined Radio with an optimized Direct Digital Frequency Synthesizer
Abstract— A Software Defined Radio (SDR) is a transmitter and receiver system that uses digital signal processing (DSP) for coding, decoding, modulating, and demodulating data. This paper presents the framework for hardware implementation of SDR using Orthogonal Frequency Division Multiplexing (OFDM). The framework comprises of VLSI mapping of algorithms, Orthogonal Frequency Division Multiplexing(OFDM), Quadrature Phase Shift Keying (QPSK), Fast Fourier Transform (FFT) Algorithms and most importantly, the algorithm for Direct Digital Frequency Synthesis (DDFS). A digital frequency synthesizer with optimized time and area resources has been proposed for the SDR. This VLSI implementation of the DDFS computes the sine and cosine function on a single edge of clock, thus proving to be optimized in terms of area and speed. Fixed-Point implementation was accomplished with ModelSim simulator. Verilog HDL was used as a description language for mapping Algorithms in VLSI. Xilinx Spartan 3 XC3S200 Field Programmable Gate Array (FPGA) was chosen as a Hardware Platform for the System Implementation.
38. FPGA based Area optimized and efficient Architecture for NMS and Thresholding used for Canny Edge Detector
Abstract—— In this paper, we present an architecture for Non Maximal Suppression used in Canny edge detection algorithm that results in significantly reduced memory requirements decreased latency and increased throughput with no loss in edge detection. The new algorithm uses a low-complexity 8-bin non-uniform gradient magnitude histogram to compute block-based hysteresis thresholds that are used by the Canny edge detector. Furthermore, FPGA-based hardware architecture of our proposed algorithm is presented in this paper and the architecture is synthesized on the Xilinx Virtex 5 FPGA. The design development is done in VHDL and simulates the results in modelsim 6.3 using Xilinx 12.2.
39. Self-Programmable Multipurpose Digital Filter Design Based on FPGA
Abstract: Conventional digital filter can only obtain fixed frequency domain characteristics at a time. In order to obtain variable characteristics, the digital filter’s type, number of taps and coefficients should be changed constantly such that the desired frequency-domain characteristics can be obtained. This paper proposes method for self-programmable Variable Digital Filter (VDF) design based on FPGA. Taking finite impulse response (FIR) digital filter as an example, we implement a digital filter system by using Custom embedded Micro-Processor, programmable FIR macro module, coefficient-loader, clock manager and A/D or D/A controller and other modules. The self-programmable VDF can provide the best solution for realization of digital filter algorithms, which are the low-pass, high-pass, band-pass and band-stop filter algorithms with variable frequency domain characteristics. The design examples with minimum 1 to maximum 32 taps FIR filter, based on Modelsim post-routed simulation and onboard running on XUPV5-LX110T, are provided to demonstrate the effectiveness of the proposed method and the online-adaptability of variable digital filters.
40. FPGA-based reconfigurable control for fault tolerant Back-to-back converter without redundancy
Abstract— In this paper, an FPGA-based fault tolerant back-to-back converter without redundancy is studied. Before fault occurrence, the fault tolerant converter operates like a conventional back-to-back six-leg converter and after the fault it becomes a five-leg converter. Design, implementation and experimental verification of an FPGA-based reconfigurable control strategy for this converter are discussed. This reconfigurable control strategy allows the continuous operation of the converter with minimum affection from a fault in one of the semiconductor switches. A very fast detection scheme is used to detect and locate the fault. Implementation of the fault detection and of the fully digital control schemes on a single FPGA is realized, based on a suited methodology for rapid prototyping. FPGA in loop and also experimental tests are carried out and the results are presented. These results confirm the capability of the proposed reconfigurable control and fault tolerant structure.
41. Reliable On-Chip Network Design Using an Agent-based Management Method
Abstract—As the complexity of evolving integrated circuits and the number of cores in each chip increase, reliability aspects are becoming an important issue in complex chip designs. In this paper, we present an on-chip network architecture that incorporates a novel agent-based management method to enhance the reliability and performance of network-based Chip Multi-Processor (CMP) and System-on Chip (SoC) designs against faulty links and routers. In addition, to utilize the fault information required for the routing process in a scalable manner, we classify the fault information to be exploited in the proposed distributed and hierarchical management structure. The experimental results show that the proposed architecture incurs only a small hardware overhead.
42. Advanced Cryptographic System for data Encryption and Decryption
Abstract– in this paper, we mainly focus on the implementation of Advanced Cryptographic System using two crypto algorithms in a single chip to provide high security and high performance. This paper proves the confidentiality of data over insecure medium. The two algorithms namely 128-bit AES and RSA implemented in a single chip prove difficult for the hacker to crack the system. It combines two transformations of AES algorithms which achieves high speed and less area on chip. This system generates keys internally, which also achieves high security and high performance with faster execution of the algorithm.
43. Mapping FPGA to Field Programmable neural Network Array (FPNNA)
Abstract: My paper presents the implementation of a generalized back-propagation multilayer perceptron (MLP) architecture, on FPGA, described in VLSI hardware description language (VHDL). The development of hardware platforms is not very economical because of the high hardware cost and quantity of the arithmetic operations required in online artificial neural networks (ANNs), i.e., general purpose ANNs with learning capability. Besides, there remains a dearth of hardware platforms for design space exploration, fast prototyping, and testing of these networks. Our general purpose architecture seeks to fill that gap and at the same time serve as a tool to gain a better understanding of issues unique to ANNs implemented in hardware, particularly using field programmable gate array (FPGA).This work describes a platform that offers a high degree of parameterization, while maintaining generalized network design with performance comparable to other hardware-based MLP implementations. Application of the hardware implementation of ANN with back-propagation learning algorithm for a realistic application is also presented.
44. Design and Implementation of Reed Solomon Decoder for 802.16 Network using FPGA
Abstract—This paper presents a design and FPGA implementation of a reconfigurable FEC Decoder based on Reed Solomon Code for WiMax Network. The implementation, written in Very High Speed hardware description Language (VHDL) is based on Berlekamp Massey, Forney and Chein Algorithm. The
802.16 network standards recommend the use of Reed-Solomon code RS (255,239), which is implemented and discussed in this paper. It is targeted to be applied in a forward error correction system based on 802.16 network standard to improve the overall performance of the system. The objective of this work is to implement a Reed- Solomon VHDL code to measure the performance of the RS Decoder on Xilinx Virtex II pro (xc2vp50- 5-ff1148) and Xilinx Spartan 3e (xc3s500e-4-fg320) FPGA Them performance of the implemented RS codec on both FPGAs will be compared .The performance metrics to be used are the area occupied by the design and the speed at which the design can run.
45. Wavelet-Based SC-FDMA System
ABSTRACT: Recent research has shown that the Single Carrier Frequency Division Multiple Access (SC-FDMA) is an attractive technology for uplink broadband wireless communications, because it does not have the problems of Orthogonal Frequency Division Multiple Access (OFDMA) such as the large Peak-to-Average Power Ratio (PAPR). In this paper, an efficient transceiver scheme for the SC-FDMA systems, using the wavelet transform is proposed. In the proposed scheme, the Fast Fourier Transform (FFT) and its inverse (IFFT) are replaced by the Discrete Wavelet Transform (DWT) and its inverse (IDWT). Wavelet filter banks at the transmitter and the receiver have the ability to reduce distortion in the reconstructed signals, while retaining all the significant features present in the signals. The performance of the proposed scheme is investigated with different wireless channels. Simulation results show that the proposed scheme provides better performance, when compared to the conventional SC-FDMA, while the complexity of the system is slightly increased.
46. An Improved VLSI Architecture of S-box for AES Encryption
Abstract—This paper presents an improved VLSI architecture of S-box for AES encryption system. Certain basic blocks in conventional architecture are replaced by efficient multiplexers and an optimized combinational logic to facilitate speed improvement. The proposed as well as conventional architecture are implemented in Xilinx FPGA and 0.18 μm standard cell ASIC technology. ASIC implementation indicates speed enhancement while maintaining constant area compared to conventional architecture. FPGA implementation also confirms speed improvement of about 0.6 ns along with low utilization of FPGA fabrics. Furthermore, there is significant power improvement (155 %) compared to conventional structure.
47. FPGA Based Design and Implementation of Modified Viterbi Decoder for a Wi-Fi Receiver
Abstract— Viterbi Decoders are employed in digital wireless communication systems to decode the convolution codes which are the forward error correcting codes. Although widely-used, the most popular communications decoding algorithm, the Viterbi Algorithm (VA), requires an exponential increase in hardware complexity to achieve greater decode accuracy. When the applications based with wireless technology has been developed tremendously with the world. The constraint length associated with the input bits are large, hence it needs to implement the larger constraint length with lesser hardware and lesser computations for decode the original data. When the decoding process uses the Modified Viterbi Algorithm (MVA) computations 50% reduced and reduction in the hardware utilization, which follows the maximum- likelihood path. It shows plan ahead associated with the modified Viterbi decoder implementation using Xilinx tool in verilog design. An implementation on Field Programmable Gate Arrays (FPGA) provides user flexibility to a programmable solutions and lowering the cost.
48. VLSI Architecture for a Reconfigurable Spectrally Efficient FDM Baseband Transmitter
Abstract—Spectrally efficient FDM (SEFDM) systems employ non-orthogonal overlapped carriers to improve spectral efficiency for future communication systems. One of the key research challenges for SEFDM systems is to demonstrate efficient hardware implementations for transmitters and receivers. Focusing on transmitters,this paper explains the SEFDM concept and examines the complexity of published modulation algorithms, with particular consideration to implementation issues. We then present two new variants of a digital baseband transmitter architecture for SEFDM, based on a modulation algorithm which employs the discrete Fourier transform (DFT) implemented efficiently using the fast Fourier transform (FFT). The algorithm requires multiple FFTs, which can be configured either as parallel transforms, which is optimal for throughput or using a multi-stream FFT architecture, for reduced circuit area. We propose a simplified approach to IFFT pruning for pipeline architectures, based on a token-flow control style, specifically optimized for the SEFDM application. Reconfigurable implementations for different bandwidth compression ratios, including conventional OFDM, are easily derived from the proposed implementations. The SEFDM transmitters have been synthesized, placed and routed in a commercial 32 nm CMOS process technology and also verified in FPGA. We report circuit area and simulated power dissipation figures, which confirm the feasibility of SEFDM transmitters.
49. Research and Implementation of Speaker Recognition Algorithm Based on FPGA
Abstract: As one of biometric identification technologies, speaker recognition shows better application prospects in many fields. At present, the implementation of speaker recognition algorithm on the hardware is mostly based on System on a Programmable Chip(SOPC) platform of Field Programmable Gate Array(FPGA) with Nios II Intellectual Property(IP) core. And the algorithm can be selected and optimized effectively on SOPC. However the high-speed and parallel operation of FPGA can’t be fully utilized. By researching and analyzing the speaker recognition algorithm, a FPGA-based speaker recognition method is presented in this paper. This method includes the Voice Active Detection (VAD), Mel Frequency Cepstrum Coefficient (MFCC) extraction and Vector Quantization (VQ) recognition algorithm. By using the technology such as Ping-pang operation, Pipeline and module reuse, it makes full use of FPGA’s speed. After testing, this method can effectively meet the requirement of real-time data processing.
50. Efficient Window-Architecture Design using Completely Scaling-Free CORDIC Pipeline
Abstract—Filtering being one of the most important modules in signal processing paradigm, this paper presents an FPGA implementation of various window-functions using CORDIC algorithm to minimize area-delay product. The existing window architecture uses a linear CORDIC processor in series with circular CORDIC processor that results in a long pipeline. Firstly, we replace the linear CORDIC with multiple optimized shift-add networks to reduce area and pipeline depth. Secondly, the conventional circular CORDIC processor is replaced by a completely scaling-free CORDIC processor to further improve the area-time efficiency of the existing design. As a result, the proposed window-architecture, on an average requires approximately 64.34% less pipeline stages and saves upto 48% area. Both the existing and the proposed window-architecture are capable of generating Hanning, Hamming and Blackman window families.
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- IR BASED AMBULANCE DETECTION IN TRAFFIC
- CAR PARKING SYSTEM USING LDR
- ARM BASED HOME APPLIANCES CONTROL
- ELECTRONIC NOTICE BOARD FOR REAL TIME APPLICATION USING LCD MONITOR
- AUTOMATIC IRRIGATION SYSTEM FOR REAL TIME DEMO
- PIR BASED HUMAN DETECTION WITH COUNT DISPLAY
- GPS DATA LOGGER WITH CAMERA TRIGGERED DATA STORING
- FLEX SENSOR BASED GESTURE VOCALIZER
- DIALY SMS REPORT BASED PREPAID ENERGY METER
- RF BASED INTERCOMMUNICATION OF TRAINS TO AVOID COLLISION
- SOLAR PANEL CONTROLLER AND POWER OPTIMIZATION
- POWER CONVERSION (AC to DC)
- TRAIN COLLISION AVOIDENCE USING VIBRATION SENSOR & MICRO-CONTROLLER.
- AUTOMATIC CONTROL OF STUDENTS ATTENDANCE IN CLASSROOMS USING RFID
- RFID BASED EMPLOYEE DATABASE MANAGEMENT USING RTC
- RFID BASED ATM WITH RANDOM PASSWORD AS AN SMS.
- WIRELESS TRANSFORMER PARAMETER MEASUREMENT AND PROTECTION
- SEEDING AGRICULTURE ROBOT
- STUDENT ENQUIRY SYSTEM BASED ON GSM
- LAND ROVER
- FLEX SENSOR USING ROBOT CONTROL
- ZIGBEE WIRELESS POWER MANAGEMENT UNIT FOR ENERGY METER
- AUTOMATED CAR PARKING USING ULTRASONIC SENSOR
- FREE MOVING ROBOT WITH FRONT & BACK IR OBSTACLE DETECTOR
- AXIS STEPPER MOTOR CONTROL FOR SOLAR PANEL WITH POWER OPTIMIZATION
- HEAD MOVEMENT BASED DEVICE CONTROL USING ZIBGEE
- Blind alert system using flex sensors
- INTELLIGENT AMBULANCE FOR CITY TRAFFIC
- WIRELESS SECURITY SYSTEM FOR HOME AUTOMATION
- BLACK MONEY TRACKER
- HITECH JAIL
- AUTOMATIC RAILWAY GATE CONTROL USING STEPPER MOTOR
- DC MOTOR SPEED MEASUREMENT
- REMOTE TEMPERATURE AND HUMIDITY MONITORING
- COMPONENT TESTER CONFIRMATION
- AUTOMATIC STREET LIGHT SENSOR WITH SMS ERROR REPORT
- CELL PHONE CONTROLLED ROBOT
- PC CONTROLLED ROBOT
- PATIENT MONITORING SYSTEM FOR BODY TEMPERATURE AND HEART RATE
- HUMAN MOTION & GAS LEAKAGE DETECTION WITH SMS INTIMATION
- ALCOHOL DETECTION IN VEHICLE
- MOBILE DETECTION
- IR BASED STREET LIGHT CONTROL
- ULTRASONIC BASED DEFENCE SECURITY SYSTEM
- BANK LOCKER SECURITY SYSTEM USING DTMF & GSM
- RF BASED ROBOT CONTROL WITH TEMPERATURE ALERT
- IR BASED OBSTACLE DETECTION ROBOT
- HOME APPLIANCE CONTROL USING RF
- INDUSTRIAL TIMER
- TRUCK LIFT INDICATOR USING ACCELEROMETER
- LDR BASED DC MOTOR ROTATION CONTROL
- RADIO CONTROLLED COMBAT ROBOT
- ACCIDENT DETECTION SYSTEM
- ELECTRONIC COUNTER WITH PLAYER JAM KEYS
- AUTOMATIC MULTISTOREY PARKING SYSTEM
- RTC BASED DEVICE CONTROL WITH START AND END TIME SET
- GPS BASED MASTER CLOCK
- MOBILE BUS RESERVATION SYSTEM
- INDUSTRIAL BATCH COUNTER FOR PACKING AUTOMATION
- PASSWORD BASED DEVICE CONTROL
- VEHICLE ASSET TOUCH DETECION USING SENSORS TECHNOLOGY WITH SMS ALERT
- AUTHORISED CREDIT CARD TRANSACTION USING BIOMETRIC SENSOR
- DEVICE CONTROL BASED ON TIMER SET VALUE
- ELECTRONIC CODE LOCK USING DTMF KEYPAD
- AUTOMATIC IRRIGATION CONTROL WITH SMS ALERT
- MICROCONTROLLER BASED INDUSTRIAL SAFETY SYSTEM
- AUTOMATIC SPEED BREAKING SYSTEMS FOR VEHICLES
- SNAKE ROBOT
- MAZE ROBOT
- MICROCONTROLLER BASED MOISTURE & LIGHT CONTROL SYSTEM FOR GARDEN
- MICROCONTROLLER BASED AUTO COLLEGE BELL WITH SPEAKER ANNOUNCEMENT
- AUTOMATIC STATION NAME DISPLAY IN TRAIN BY USING IR
- FUEL INDICATION & PETROL BUNK DETECTOR
- SMS BASED DC MOTOR SPEED CONTROL
- SMS BASED AC MOTOR SPEED CONTROL
- DISTANCE MEASUREMENT USING ULTRASONIC TECHNOLOGY
- RTC BASED DIGITAL COUNTDOWN TIMER
- RTC BASED DIGITAL CALENDAR
- EARTHQUAKE DISASTER RESCUE ROBOT
- SMS BASED NOTICE BOARD USING GSM & LCD WITH PERIOD BELL
- INTELLIGENT ENERGY SAVING SYSTEM IN LIBRARIES
- STREET LIGHT POWER SAVER
- VEHICLE CONTROL UNDER DRIVER FATIGUE
- AUTOMATIC DRUCKEN DRIVE AVOIDING SYSTEM
- BLACK BOX IMPLEMENTATION FOR VEHICLE
- PLANET ROVER
- GREENHOUSE MAINTAINANCE SYSTEM USING PIC
- IR BASED WALKING STICK FOR BLIND
- DENSITY BASED TRAFFIC SIGNAL CONTROL
- SMS BASED AC CONTROL
- HOME SECURITY SYSTEM
- MULTI PURPOSE SECURITY SYSTEM USING GSM
- REMOTE FIRING ROBOT
- VOICE OPERATED SYSTEM
- HW Simulated Phase Meter
- RF BASED HEART RATE MONITOR
- Toll Collection System using RFID
- Metal Detecting Robot
- PICK AND PLACE ROBOT
- RF BASED PICK AND PLACE ROBOT
- SMART PARKING SYSTEM
- SMS BASED IRRIGATION SYSTEM
- DTMF CONTROLLED ROBOT
- AC ENERGY SAVER
- RFID BASED VOTING MACHINE
- RF BASED WATER LEVEL CONTROLLER
- LED DISPLAY BOARD WITH DATA UPDATER
- FIRE SENSING ROBOT WITH RF AND ALARM
- LASER SECURITY SYSTEM
- AUTOMATIC OBJECT IDENTIFIER
- LINE FOLLOWER ROBOT
- IMPLEMENTING PERIPHERALS USING 8051 MICROCONTROLLER
- LIBRARY DATA MANAGING DEVICE
- AUTOMATIC DOOR OPENING USING PIR
- HIGHWAY VEHICLE TRAFFIC MONITER USING GSM
- VEHICLE TRACKING USING GPS AND GSM
- HOME SECURITY AND AUTOMATION USING GSM
- INDUSTRIAL COOLING SYSTEM
- AUTOMATIC LIGHTNING AND COOLING SYSTEM
- SMS BASED NOTICE BOARD USING GSM
- RF BASED TEMPERATURE AND HUMIDITY MONITORING SYSTEM
- RFID BASED OFFICE SECURITY SYSTEM
- EVENT MANAGEMENT MONITORING SYSTEM
- WIRELESS ROBOT MONITERING USING RF
- WIRELESS DOOR MONITERING
- SMS BASED HOME AUTOMATION
- AUTOMATIC HIGHWAY SIGNALLING SYSTEM
- AUTOMATIC HIGHWAY SIGNALLING SYSTEM USING ZIGBEE
- IR BASED OBSTACLE DETECTOR
- RFID and ZIGBEE BASED LIBRARY MANAGEMENT
- AUTOMATIC RAILWAY SIGNALLING SYSTEM
|IEEE 2013 B.E/M.Tech Final year Projects|
|Nonlocally Centralized Sparse Representation for Image Restoration Apr 13|
|Sparse Representation based Image Interpolation with Nonlocal Autoregressive Modeling Apr 13|
|Removing Atmospheric Turbulence via Space-Invariant Deconvolution Jan 13|
|SAIF-ly Boost Denoising Performance Apr 2013|
|IEEE 2012 B.E/M.Tech Final year Projects|
|Monotonic Regression: A New Way for Correlating Subjective and Objective Ratings in Image Quality Research|
|Image Signature: Highlighting Sparse Salient Regions|
|Nonparametric Bayesian Dictionary Learning for Analysis of Noisy and Incomplete Images|
|Patch-Based Near-Optimal Image Denoising|
|Accelerated Hypothesis Generation for Multistructure Data via Preference Analysis|
|BM3D Frames and Variational Image Deblurring.|
|Re-initialization Free Level Set Evolution via Reaction Diffusion Dec 2012|
|Monogenic Binary Coding: An Efficient Local Feature Extraction Approach to Face Recognition Sep 2012|
|On Optimal Power Control for Delay-Constrained Communication over Fading Channels IEEE 2011|
|Performance analysis of channel estimation and adaptive equalization in slow fading channel|
|Communication Based B.E/M.Tech mini project|
|Fast and accurate sequential floating forward feature selection withthe Bayes classifier applied to speech emotion recognition||speech|
|Demonstration of Real-time Spectrum Sensing for Cognitive Radio||FFT,Radio|
|ML Estimation of Time and Frequency Offset in OFDM Systems||OFDM|
|Efficient Encoding of Low-Density Parity-Check Codes||LDPC|
|Multi-User Diversity vs. Accurate Channel State Information in MIMO Downlink||MIMO|
|Sum Power Iterative Water-Filling for Multi-Antenna Gaussian Broadcast Channels||MIMO,MAC|
|On Optimal Power Control for Delay-Constrained Communication over Fading Channels||power control|
|Hybrid DE Algorithm With Adaptive Crossover Operator For Solving Real-World Numerical Optimization Problems||DE algorithm,search routine|
|An Improved Algorithm for Blind Reverberation Time Estimation||signal processing|
|Image processing B.E/M.Tech mini projects|
|Real-Time Compressive Tracking||face tracking|
|An Efficient Algorithm for Level Set Method Preserving Distance Function||segmentation|
|Efficient Misalignment-Robust Representation for Real-Time Face Recognition||face detection|
|Robust Point Matching Revisited: A Concave Optimization Approach||point matching|
|Canny Edge Detection Enhancement by Scale Multiplication||edge detection|
|ROBUST OBJECT TRACKING USING JOINT COLOR-TEXTURE HISTOGRAM||tracking|
|Distance Regularized Level Set Evolution and Its Application to Image Segmentation||segmentation|
|A Level Set Method for Image Segmentation in the Presence of Intensity Inhomogeneities With Application to MRI||biomedical|
|Minimization of Region-Scalable Fitting Energy for Image Segmentation||segmentation|
In an environment where mobile data privacy is increasingly in the headlines, this project will make it easier than ever for mobile developers to properly secure their local application data, and in turn better protect the privacy of their users.
The data stored by Android apps protected by this type of encryption will be less vulnerable to access by malicious apps, protected in case of device loss or theft, and highly resistant to mobile data forensics tools that are increasingly used to mass copy a mobile device during routine traffic stops.
SQLCipher is an SQLite extension that provides transparent 256-bit AES encryption of database files.Given that Android by default provides integrated support for SQLite databases, our goal was to create an almost identical API for SQLCipher.
100% Real Time Implementation
A user’s phone will publish the signal strength of wifi networks in the area. Other Android users will be able to view this information if a better wifi location is desired. Wifi data will be presented on a Google Map, to indicate other users’ wifi status.
1. Get wifi signal strength of the current location.
2. Read the current location in terms of longitude and latitude using the phone’s GPS hardware.
3. Read friends’ wifi signal/location history from disk.
4. Send updated wifi/location data on the server.
5. Retrieve friends’ history from the server.
6. Save this information on the disk to display it the next time the application runs. This is helpful when the user is in a place without internet access and cannot connect to the server. The most recently updated set of friends’ data will be displayed, so that a wifi connection can be located nearby.
7. Display the user history data on a Google Map, with a unique color for each user. The map will display the user’s name, the name of the wifi network with the strongest signal, and the signal strength on a scale from 0 (weakest) to 10 (strongest).
100% Real Time Implementation
It emphasizes general principles of image processing, rather than specific applications.We expect to cover topics such as image sampling and quantization, color, point operations, segmentation, morphological image processing, linear image filtering and correlation, image transforms, eigen images, multi resolution image processing, wavelets, noise reduction and restoration, feature extraction and recognition tasks, and image registration.
- Histogram Equalization
- Color Histograms
- Edges,Lines and Circles
100% Real Time Implementation